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LTC3789 High Efficiency, Synchronous, 4-Switch Buck-Boost Controller FeaTures
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DescripTion
The LTC(R)3789 is a high performance buck-boost switching regulator controller that operates from input voltages above, below or equal to the output voltage. The constant-frequency, current mode architecture allows a phase-lockable frequency of up to 600kHz, while an output current feedback loop provides support for battery charging. With a wide 4V to 38V (40V maximum) input and output range and seamless, low noise transitions between operating regions, the LTC3789 is ideal for automotive, telecom and battery-powered systems. The operating mode of the controller is determined through the MODE/PLLIN pin. The MODE/PLLIN pin can select between pulse-skipping mode and forced continuous mode operation and allows the IC to be synchronized to an external clock. Pulse-skipping mode offers the lowest ripple at light loads, while forced continuous mode operates at a constant frequency for noise-sensitive applications. A power good output pin indicates when the output is within 10% of its designed set point. The LTC3789 is available in low profile 28-pin 4mm x 5mm QFN and narrow SSOP packages.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Module and Burst Mode are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5408150, 5481178, 5929620, 6580258, 7365525, 7394231.
Single Inductor Architecture Allows VIN Above, Below or Equal to Regulated VOUT Programmable Input or Output Current Feedback Loop Wide VIN Range: 4V to 38V 1% Output Voltage Accuracy: 0.8V < VOUT < 38V Synchronous Rectification: Up to 98% Efficiency Current Mode Control Phase-Lockable Fixed Frequency: 200kHz to 600kHz No Reverse Current During Start-Up Power Good Output Voltage Monitor Internal 5.5V LDO Quad N-Channel MOSFET Synchronous Drive VOUT Disconnected from VIN During Shutdown Adjustable Soft-Start Output Ramping Available in 28-Lead QFN (4mm x 5mm) and 28-Lead SSOP Packages
applicaTions
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Automotive Systems Distributed DC Power Systems High Power Battery-Operated Devices Industrial Control
Typical applicaTion
+
4.7F ILIM VIN 4V TO 38V PGOOD 22F 50V CER A VIN VINSNS 0.1F TG1 INTVCC IOSENSE
-
1F CER IOSENSE+ EXTVCC VOUTSNS 0.1F D 10F 16V CER VOUT 12V 5A 330F 16V EFFICIENCY (%) 100 95 90 85 80 75 70
Efficiency and Power Loss
0.010 12 10 8 6 4 2 0 POWER LOSS (W)
+
TG2 LTC3789 BOOST1 BOOST2 SW1 SW2 BG2 MODE/PLLIN RUN VFB FREQ 121k ON/OFF BG1
B 2200pF 1000pF 8k 0.01F
C 105k 1% 7.5k 1%
ITH SS SGND
VOUT = 12V ILOAD = 5A 0 5 10 15 20 VIN (V) 25 30 35 40
SENSE+ SENSE- PGND
3789 TA01b
0.010
4.7H
3789 TA01
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LTC3789 absoluTe MaxiMuM raTings (Note 1)
Input Supply Voltage (VIN) ......................... 40V to -0.3V Topside Driver Voltages (BOOST1, BOOST2) .................................. 46V to -0.3V Switch Voltage (SW1, SW2) ......................... 40V to -5V Current Sense Voltages (IOSENSE+, IOSENSE-) ...40V to -0.3V BOOST1, BOOST2 - SW1, SW2 ................... 6V to -0.3V TG1, TG2 - SW1, SW2................................. 6V to -0.3V EXTVCC Voltage .......................................... 14V to -0.3V INTVCC Voltage............................................. 6V to -0.3V SENSE+, SENSE- Voltages .................... INTVCC to -0.3V MODE/PLLIN, SS Voltages ................... INTVCC to -0.3V VINSNS, VOUTSNS ......................................... 40V to -0.3V BG1, BG2 Voltages ............................... INTVCC to -0.3V ITH, FREQ, ILIM Voltages........................ INTVCC to -0.3V VFB Voltage................................................ 2.7V to -0.3V RUN, PGOOD Voltage ................................. 6V to -0.3V Operating Junction Temperature Range (Notes 2, 3) ............................................ -40C to 125C Storage Temperature Range................... -65C to 125C INTVCC Peak Output Current ................................100mA Lead Temperature (Soldering, 10 sec.) GN Package...................................................... 300C
pin conFiguraTion
TOP VIEW SENSE+ VFB SS SENSE+ SENSE - ITH SGND MODE/PLLIN FREQ RUN 1 2 3 4 5 6 7 8 9 28 PGOOD 27 SW1 26 TG1 25 BOOST1 24 PGND 23 BG1 22 VIN 21 INTVCC 20 EXTVCC 19 BG2 18 BOOST2 17 TG2 16 SW2 15 TRIM SENSE- 1 ITH 2 SGND 3 MODE/PLLIN 4 FREQ 5 RUN 6 VINSNS 7 VOUTSNS 8 9 10 11 12 13 14 IOSENSE+ ILIM
-
TOP VIEW PGOOD SW1 SW2 TG1 22 BOOST1 21 PGND 20 BG1 29 SGND 19 VIN 18 INTVCC 17 EXTVCC 16 BG2 15 BOOST2 TRIM TG2 VFB IOSENSE
28 27 26 25 24 23
VINSNS 10 VOUTSNS 11 ILIM 12 IOSENSE+ 13 IOSENSE- 14
GN PACKAGE 28-LEAD NARROW PLASTIC SSOP TJMAX = 125C, JA = 80C/W
UFD PACKAGE 28-LEAD (4mm x 5mm) PLASTIC QFN TJMAX = 125C, JA = 34C/W EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH LTC3789EGN#PBF LTC3789IGN#PBF LTC3789EUFD#PBF LTC3789IUFD#PBF TAPE AND REEL LTC3789EGN#TRPBF LTC3789IGN#TRPBF LTC3789EUFD#TRPBF LTC3789IUFD#TRPBF PART MARKING* LTC3789 LTC3789 3789 3789 PACKAGE DESCRIPTION 28-Lead Narrow Plastic SSOP 28-Lead Narrow Plastic SSOP 28-Lead (4mm x 5mm) Plastic QFN 28-Lead (4mm x 5mm) Plastic QFN TEMPERATURE RANGE -40C to 125C -40C to 125C -40C to 125C -40C to 125C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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SS
LTC3789 elecTrical characTerisTics
SYMBOL VIN VOUT VFB IFB VREFLNREG VLOADREG gm IQ UVLO UVLO Hyst ISENSE+ ISENSE- IIOSENSE+ IIOSENSE- ISS VRUN(ON) VRUN(HYS) IRUN IRUN(HYS) VSENSE(MAX) VSENSE(IAVG) RDSPFET(ON) RDSNFET(ON) TG tr TG tf BG tr BG tf TG/BG t1D BG/TG t1D DFMAX,BOOST DON(MIN,BOOST) DON(MIN,BUCK) PARAMETER Input Supply Voltage Output Voltage Regulated Feedback Voltage Feedback Current Reference Voltage Line Regulation Output Voltage Load Regulation ITH Voltage = 1.2V (Note 4), TA = -40C to 85C ITH = 1.2V, TA = 125C, TA = -40C to 125C (Note 4) VIN = 4V to 38V (Note 4) (Note 4) Measured in Servo Loop, ITH Voltage = 1.4V to 2V Measured in Servo Loop, ITH Voltage = 2V to 2.6V ITH = 1.2V, Sink/Source 5A (Note 4) (Note 5) VRUN = 0V INTVCC Ramping Down VSENSE- = VSENSE+ = 0V VIOSENSE- = VIOSENSE+ = 10V VSS = 0V VRUN Rising 2
l l l l
The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C (Note 2). VIN = 15V, VRUN = 5V, unless otherwise noted.
CONDITIONS MIN 4 0.8 0.792 0.788 0.800 0.800 -15 0.002 0.01 -0.01 1.5 3 40 3.4 0.4 0.2 10 3 1.22 150 1.2 5
l l
TYP
MAX 38 38 0.808 0.812 -50 0.02 0.1 -0.1
UNITS V V V V nA %/V % % mmho mA A V V A A A V mV A A
Transconductance Amplifier gm Input DC Supply Current Normal Mode Shutdown Undervoltage Lockout Undervoltage Hysteresis SENSE Pins Current IOSENSE Pins Current Soft-Start Charge Current RUN Pin On-Threshold RUN Pin On-Hysteresis RUN Pin Source Current RUN Pin Hysteresis Current
60 3.6 1 14 4
Maximum Current Sense Threshold VFB = 0.7V Buck Region Boost Region VFB = 0.7V Maximum Input/Output Average Current Sense Threshold Driver Pull-Up On-Resistance Driver Pull-Down On-Resistance Top Gate Rise Time Top Gate Fall Time Bottom Gate Rise Time Bottom Gate Fall Time Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time Maximum Duty Factor Minimum Duty Factor for Main Switch in Boost Operation Minimum Duty Factor for Main Switch in Buck Operation CLOAD = 3300pF Each Driver (Note 6) CLOAD = 3300pF Each Driver (Note 6) % Switch C On % Switch C On % Switch B On ILIM = 0V ILIM Floating ILIM = INTVCC
60 110 47 90 130
90 140 50 100 145 2.6 1.5 25 25 25 25 60
110 165 53 106 160
mV mV mV mV mV ns ns ns ns ns
60 90 9 9
ns % % %
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LTC3789 elecTrical characTerisTics
SYMBOL VINTVCCVIN VLDOVIN VINTVCCEXT VLDOEXT VEXTVCC VLDOHYS fNOM fLOW fHIGH fSYNC RMODE/PLLIN IFREQ PGOOD Output VPGL IPGOOD VPG PGOOD Voltage Low PGOOD Leakage Current PGOOD Trip Level IPGOOD = 2mA VPGOOD = 5V VFB with Respect to Set Output Voltage VFB Ramping Negative VFB Ramping Positive -10 10 0.1 0.3 1 V A % % PARAMETER Internal VCC Voltage INTVCC Load Regulation Internal VCC Voltage INTVCC Load Regulation EXTVCC Switchover Voltage EXTVCC Hysteresis Nominal Frequency Low Fixed Frequency High Fixed Frequency Synchronizable Frequency MODE/PLLIN Input Resistance Frequency Setting Current 8 VFREQ = 1.2V, RFREQ = 1.22k VFREQ = 0V VFREQ = 2.4V MODE/PLLIN = External Clock
l
The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C (Note 2). VIN = 15V, VRUN = 5V, unless otherwise noted.
CONDITIONS 6.5V < VIN < 40V, VEXTVCC = 0V ICC = 0mA to 20mA, VEXTVCC = 0V 6.5V < VEXTVCC < 14V ICC = 0mA to 20mA, VEXTVCC = 12V ICC = 0mA to 20mA, EXTVCC Ramping Positive 4.7 5.2 MIN 5.2 TYP 5.5 0.2 5.5 0.2 4.8 0.25 350 175 570 200 220 10 12 400 200 640 440 225 710 600 MAX 5.8 1.0 5.8 1.0 UNITS V % V % V V kHz kHz kHz kHz k A
INTVCC Linear Regulator
Oscillator and Phase-Locked Loop
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3789 is tested under pulse load conditions such that TJ TA. The LTC3789E is guaranteed to meet performance specifications from 0C to 85C operating junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3789I is guaranteed to meet performance specifications over the full -40C to 125C operating junction temperature range.
Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC3789GN: TJ = TA + (PD * 80C/W) LTC3789UFD: TJ = TA + (PD * 34C/W) Note 4: The LTC3789 is tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VFB. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See the Applications Information section.
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LTC3789 Typical perForMance characTerisTics TA = 25C unless otherwise noted.
Efficiency vs Output Current (Boost Region)
100 90 80 EFFICIENCY (%) EFFICIENCY (%) 70 60 50 40 30 20 10 0 10 CIRCUIT OF FIGURE 13 100 1000 LOAD CURRENT (mA) DCM FCM 10000
3789 G01
Efficiency vs Output Current (Buck-Boost Region)
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 10 CIRCUIT OF FIGURE 13 100 1000 LOAD CURRENT (mA) DCM FCM 10000
3789 G02
Efficiency vs Output Current (Buck Region)
100 90 80 70 60 50 40 30 20 10 0 10 CIRCUIT OF FIGURE 13 100 1000 LOAD CURRENT (mA) DCM FCM 10000
3789 G03
VIN = 6V VOUT = 12V
VIN = 12V VOUT = 12V
VIN = 18V VOUT = 12V
99 98 97
Efficiency vs VIN
CIRCUIT OF FIGURE 13 6.0
Internal 5.5V LDO Line Regulation
6 5 4 INTVCC (V)
5.0
EXTVCC LDO Line Regulation
5.5 INTVCC VOLTAGE (V)
EFFICIENCY (%)
96 95 94 93 92 91 0 10 20 VIN (V) FREQUENCY 200kHz 300kHz 400kHz 520kHz 30 40
3789 G04
3 2 1 0
4.5
4.0
3.5
4
9
24 19 14 29 INPUT VOLTAGE (V)
34
3789 G05
4
5
6
7
8
9
10 11 12 13 14
3789 G06
EXTVCC (V)
INTVCC and EXTVCC Switch Voltage vs Temperature
6 INTVCC AND EXTVCC SWITCH VOLTAGE (V) 5 4 3 2 1 0 20 40 60 -60 -40 -20 0 TEMPERATURE (C) RISING FALLING
SUPPLY CURRENT (mA) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
Supply Current vs Input Voltage
UNDERVOLTAGE RESET VOLTAGE AT RUN (V) 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6
RUN Pin Threshold vs Temperature
RISING FALLING
80
100
3789 G07
4
9
24 14 19 29 INPUT VOLTAGE (V)
34
3789 G08
0.5 20 40 60 -60 -40 -20 0 TEMPERATURE (C)
80
100
3789 G09
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LTC3789 Typical perForMance characTerisTics TA = 25C unless otherwise noted.
Forced Continuous Mode
SW1 10V/DIV SW2 10V/DIV IL 1A/DIV IL 1A/DIV SW1 10V/DIV SW2 10V/DIV
Forced Continuous Mode
SW1 10V/DIV SW2 10V/DIV
Forced Continuous Mode
IL 1A/DIV
VIN = 6V VOUT = 12V
4s/DIV
3789 G10
VIN = 12V VOUT = 12V
4s/DIV
3789 G11
VIN = 18V VOUT = 12V
4s/DIV
3789 G12
Pulse-Skipping Mode
SW1 10V/DIV SW2 10V/DIV SW1 10V/DIV SW2 10V/DIV
Pulse-Skipping Mode
SW1 10V/DIV SW2 10V/DIV
Pulse-Skipping Mode
IL 1A/DIV 4s/DIV
3789 G13
IL 1A/DIV 2s/DIV
3789 G14
IL 1A/DIV
VIN = 12V VOUT = 12V
VIN = 6V VOUT = 12V
VIN = 18V VOUT = 12V
2s/DIV
3789 G15
Oscillator Frequency vs Temperature
700 OSCILLATOR FREQUENCY (kHz) 600 VFREQ = 2.4V
Undervoltage Threshold at INTVCC vs Temperature
5.0 4.5 4.0 RISING UNDERVOLTAGE (V) FALLING 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 20 40 60 -60 -40 -20 0 TEMPERATURE (C) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 80 100
3789 G17
Undervoltage Threshold at VIN vs Temperature
RISING FALLING
400 300 200 100 0 -50 0
VFREQ = 1.2V
VFREQ = 0V
UNDERVOLTAGE (V)
500
50 100 TEMPERATURE (C)
150
3789 G16
0 20 40 60 -60 -40 -20 0 TEMPERATURE (C)
80
100
3789 G18
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LTC3789 Typical perForMance characTerisTics TA = 25C unless otherwise noted.
Maximum Current Sense Threshold vs Duty Factor (Boost)
150 140 130 CURRENT LIMIT (mV) 120 110 100 90 80 70 60 50 0 20 60 40 DUTY FACTOR (%) 80 100
3789 G19
Maximum Current Sense Threshold vs Duty Factor (Buck)
150 140 130 CURRENT LIMIT (mV) 120 110 100 90 80 70 60 50 0 20 60 40 DUTY FACTOR (%) 80 100
3789 G20
Maximum Current Limit vs Temperature
150 MAXIMUM CURRENT LIMIT (mV) 140 130 120 110 100 90 80 70 60 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C) 3789 G21 BUCK BOOST
Peak Current Threshold vs VITH (Boost)
200 150 CURRENT LIMIT (mV)
Valley Current Threshold vs VITH (Buck)
200 150 CURRENT LIMIT (mV) 100 50 0 -50 -100
Current Foldback Limit
160 140 CURRENT LIMIT (mV) 120 100 80 60 40 20
100 50 0 -50
-100 -150
-200
0
0.5
1
1.5 VITH (V)
2
2.5
3
3789 G22
0
0.5
1
1.5 VITH (V)
2
2.5
3789 G23
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VFB (V)
3789 G24
Load Step
VOUT 200mV/DIV VOUT 200mV/DIV
Load Step
VOUT 200mV/DIV
Load Step
IL 2A/DIV 400s/DIV VIN = 6V VOUT = 12V LOAD STEP = 200mA TO 2A
3789 G25
IL 2A/DIV 400s/DIV VIN = 12V VOUT = 12V LOAD STEP = 300mA TO 3A
3789 G26
IL 2A/DIV 400s/DIV VIN = 18V VOUT = 12V LOAD STEP = 300mA TO 3A
3789 G27
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LTC3789 Typical perForMance characTerisTics TA = 25C unless otherwise noted.
Line Transient
VITH VIN 30V TO 5V VITH
Line Transient
VIN 5V TO 30V VOUT (AC) 500mV/DIV IL 2A/DIV
VOUT (AC) 500mV/DIV IL 2A/DIV
1ms/DIV
3789 G28
1ms/DIV
3789 G29
pin FuncTions
(SSOP/QFN)
VFB (Pin 1/Pin 26): Error Amplifier Feedback Pin. Receives the feedback voltage for the controller from an external resistive divider across the output. SS (Pin 2/Pin 27): External Soft-Start Input. The LTC3789 regulates the VFB voltage to the smaller of 0.8V or the voltage on the SS pin. A internal 3A pull-up current source is connected to this pin. A capacitor to ground at this pin sets the ramp time to final regulated output voltage. SENSE+ (Pin 3/Pin 28): The (+) Input to the Current Sense Comparator. The ITH pin voltage and controlled offsets between the SENSE- and SENSE+ pins, in conjunction with RSENSE , set the current trip threshold. SENSE- (Pin 4/Pin 1): The (-) Input to the Current Sense Comparator. ITH (Pin 5/Pin 2): Error Amplifier Output and Switching Regulator Compensation Point. The channel's current comparator trip point increases with this control voltage. SGND (Pin 6/Pins 3, Exposed Pad Pin 29): Small Signal Ground. Must be routed separately from high current grounds to the common (-) terminals of the CIN capacitors. In the QFN package, the exposed pad is SGND. It must be soldered to PCB ground for rated thermal performance.
MODE/PLLIN (Pin 7/Pin 4): Mode Selection or External Synchronization Input to Phase Detector. This is a dualpurpose pin. When external frequency synchronization is not used, this pin selects the operating mode. The pin can be tied to SGND or INTVCC. SGND or below 0.8V enables forced continuous mode. INTVCC enables pulse-skipping mode. For external sync, apply a clock signal to this pin; the internal PLL will synchronize the internal oscillator to the clock. The PLL composition network is integrated into the IC. FREQ (Pin 8/Pin 5): Frequency Set Pin. There is a precision 10A current flowing out of this pin. A resistor to ground sets a voltage which, in turn, programs the frequency. Alternatively, this pin can be driven with a DC voltage to vary the frequency of the internal oscillator. RUN (Pin 9/Pin 6): Run Control Input. Forcing the pin below 0.5V shuts down the controller, reducing quiescent current. There are 1.2A pull-up currents for this pin. Once the RUN pin rises above 1.22V, the IC is turned on, and an additional 5A pull-up current is added to the pin. VINSNS (Pin 10/Pin 7): VIN Sense Input to the Buck-Boost Transition Comparator. Connect this pin to the drain of the top N-channel MOSFET on the input side.
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LTC3789 pin FuncTions
(SSOP/QFN)
VOUTSNS (Pin 11/Pin 8): VOUT Sense Input to the BuckBoost Transition Comparator. Connect this pin to the drain of the top N-channel MOSFET on the output side. ILIM (Pin 12/Pin 9): Input/Output Average Current Sense Range Input. This pin tied to SGND, INTVCC or left floating, sets the maximum average current sense threshold. IOSENSE Average Current Sense Amplifier.
+ (Pin 13/Pin 10): The (+) Input to the Input/Output
BG1, BG2 (Pins 23, 19/Pins 20, 16): High Current Gate Drives for Bottom (Synchronous) N-Channel MOSFETs. Voltage swing at these pins is from ground to INTVCC. PGND (Pin 24/Pin 21): Driver Power Ground. Connects to COUT and RSENSE (-) terminal(s) of CIN. BOOST1, BOOST2 (Pins 25, 18/Pins 22, 15): Bootstrapped Supplies to the Top Side Floating Drivers. Capacitors are connected between the BOOST and SW pins and Schottky diodes are tied between the BOOST and INTVCC pins. Voltage swing at the BOOST pins is from INTVCC to (VIN + INTVCC). TG1, TG2 (Pins 26, 17/Pins 23, 14): High Current Gate Drives for Top N-Channel MOSFETs. These are the outputs of floating drivers with a voltage swing equal to INTVCC - 0.5V superimposed on the switch node voltage SW. SW1, SW2 (Pins 27, 16/Pins 24, 13): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. PGOOD (Pin 28/Pin 25): Open-Drain Logic Output. PGOOD is pulled to ground when the voltage on the VFB pin is not within 10% of its regulation window, after the internal 20s power-bad mask timer expires.
IOSENSE- (Pin 14/Pin 11): The (-) Input to the Input/Output Average Current Sense Amplifier. TRIM (Pin 15/Pin 12): Tie this pin to GND for normal operation. Do not allow this pin to float. EXTVCC (Pin 20/Pin 17): External Power Input to an Internal LDO Connected to INTVCC. This LDO supplies INTVCC power, bypassing the internal LDO powered from VIN whenever EXTVCC is higher than 4.8V. See EXTVCC Connection in the Applications Information section. Do not exceed 14V on this pin. INTVCC (Pin 21/Pin 18): Output of the Internal Linear Low Dropout Regulator. The driver and control circuits are powered from this voltage source. Must be bypassed to power ground with a minimum of 4.7F tantalum, ceramic, or other low ESR capacitor. VIN (Pin 22/Pin 19): Main Supply Pin. A bypass capacitor should be tied between this pin and the signal ground pin.
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LTC3789 block DiagraM
INTVCC BOOST1 CHARGE PUMP BOOST1 VIN CHARGE PUMP BOOST2 SW1 FCB BUCK LOGIC TG1 SW1 INTVCC BG1 PGND BG2 RSENSE VIN
+ - + -
IDREV
IREV
FCB
VFLD
BOOST LOGIC
INTVCC
SW2 TG2
+ -
1.2A SHDN SLOPE
ICMP
BOOST2 OV
+
RUN
IOSENSE+ IOSENSE- ILIM
INTVCC RSENSE2 VOUT
IOS EA
- - - - + +
+
VFB 0.80V SS
FIN
MODE/ PLLIN 220k
3A PHASE DET
10A FREQ OSCILLATOR
ITH SENSE+ SENSE- EXTVCC
VIN
VIN
4.8V EXTVCC
+ -
5.5V LDO REG 5.5V LDO REG
0.86V
VFB
+
5.5V
INTVCC INTERNAL SUPPLY 0.74V
SGND
10
+ + -
-
OV PGOOD
3789 BD
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LTC3789 operaTion
MAIN CONTROL LOOP The LTC3789 is a current mode controller that provides an output voltage above, equal to or below the input voltage. The LTC proprietary topology and control architecture employs a current-sensing resistor. The inductor current is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The VFB pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. If the input/output current regulation loop is implemented, the sensed inductor current is controlled by either the sensed feedback voltage or the input/output current. INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the EXTVCC is left open or tied to a voltage less than 4.5V, an internal 5.5V low dropout (LDO) regulator supplies INTVCC power from VIN. If EXTVCC is taken above 4.8V, the 5.5V regulator is turned off, and another LDO regulates INTVCC from EXTVCC. The EXTVCC LDO allows the INTVCC power to be derived from a high efficiency external source such as the LTC3789 regulator output. The absolute maximum voltage on EXTVCC is 14V. Internal Charge Pump Each top MOSFET driver is biased from the floating bootstrap capacitors CA and CB, which are normally recharged by INTVCC through an external diode when the top MOSFET is turned off. When the LTC3789 operates exclusively in the buck or boost regions, one of the top MOSFETs is constantly on. An internal charge pump recharges the bootstrap capacitor to compensate for the small leakage current through the bootstrap diode so that the MOSFET can be kept on. However, if a high leakage diode is used such that the internal charge pump cannot provide sufficient charges to the external bootstrap capacitor, an internal UVLO comparator, which constantly monitors the drop across the capacitor, will sense the (BOOST - SW) voltage when it is below 3.6V. It will turn off the top MOSFET for about one-twelfth of the clock period every four cycles to allow CA or CB to recharge. Shutdown and Start-Up The controller can be shut down by pulling the RUN pin low. When the RUN pin voltage is below 0.5V, the LTC3789 goes into low quiescent current mode. Releasing RUN allows an internal 1.2A current to pull up the pin and enable the controller. When RUN is above the accurate threshold of 1.22V, the internal LDO will power up the INTVCC. At the same time, a 6A pull-up current will kick in to provide more RUN pin hysteresis. The RUN pin may be externally pulled up or driven directly by logic. Be careful not to exceed the absolute maximum rating of 6V on this pin. The start-up of the controller's output voltage VOUT is controlled by the voltage on the SS pin. When the voltage on the SS pin is less than the 0.8V internal reference, the LTC3789 regulates the VFB voltage to the SS voltage instead of the 0.8V reference. This allows the SS pin to be used to program soft-start by connecting an external capacitor from the SS pin to SGND. An internal 3A pull-up current charges this capacitor, creating a voltage ramp on the SS pin. As the SS voltage rises linearly from 0V to 0.8V (and beyond), the output voltage VOUT rises smoothly from zero to its final value. Alternatively, the SS pin can be used to cause the start-up of VOUT to track that of another supply. When RUN is pulled low to disable the controller, or when INTVCC is below the undervoltage lockout threshold of 3.4V, the SS pin is pulled low by an internal MOSFET. In undervoltage lockout, the controller is disabled and the external MOSFETs are held off.
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LTC3789 operaTion
POWER SWITCH CONTROL Figure 1 shows a simplified diagram of how the four power switches are connected to the inductor, VIN, VOUT and GND. Figure 2 shows the regions of operation for the LTC3789 as a function of duty cycle, D. The power switches are properly controlled so the transfer between regions is continuous. Buck Region (VIN >> VOUT) Switch D is always on and switch C is always off in this region. At the start of every cycle, synchronous switch B is turned on first. Inductor current is sensed when synchronous switch B is turned on. After the sensed voltage falls below a reference voltage, which is proportional to VITH, synchronous switch B is turned off and switch A is turned on for the remainder of the cycle. Switches A and B will alternate, behaving like a typical synchronous buck regulator. The duty cycle of switch A increases until the maximum duty cycle of the converter reaches DMAX_BUCK, given by: Figure 3 shows typical buck region waveforms. If VIN approaches VOUT, the buck-boost region is reached.
CLOCK SWITCH A SWITCH B SWITCH C SWITCH D IL
3780 F03
LOW HIGH
Figure 3. Buck Region (VIN >> VOUT)
Buck-Boost Region (VIN VOUT) When VIN is close to VOUT , the controller enters buckboost region. Figure 4 shows the typical waveforms in this region. At the beginning of a clock cycle, if the controller starts with B and D on, the controller first operates as a buck region. When ICMP trips, switch B is turned off, and switch A is turned on. At 120 clock phase, switch C is turned on. The LTC3789 starts to operate as a boost until ICMP trips. Then, switch D is turned on for the remainder of the clock period. If the controller starts with switches A and C on, the controller first operates as a boost, until ICMP trips and switch D is turned on. At 120, switch B is turned on, making it operate as a buck. Then, ICMP trips, turning switch B off and switch A on for the remainder of the clock period. Boost Region (VIN << VOUT) Switch A is always on and synchronous switch B is always off in the boost region. In every cycle, switch C is turned on first. Inductor current is sensed when synchronous switch C is turned on. After the sensed inductor current exceeds what the reference voltage demands, which is proportional to VITH, switch C is turned off and synchronous switch D is turned on for the remainder of the cycle. Switches C and D will alternate, behaving like a typical synchronous boost regulator.
1 DMAX _ BUCK = 1- * 100% = 91.67% 12
VIN TG1 A SW1 BG1 B RSENSE
3789 F01
VOUT L D SW2 C BG2 TG2
Figure 1. Simplified Diagram of the Output Switches
90% DMAX OOST DMIN BOOST DMAX BUCK
A ON, B OFF PWM C, D SWITCHES FOUR SWITCH PWM D ON, C OFF PWM A, B SWITCHES
BOOST REGION
BUCK/BOOST REGION
BUCK REGION
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DMIN BUCK
Figure 2. Operating Region vs Duty Cycle
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LTC3789 operaTion
The duty cycle of switch C decreases until the minimum duty cycle of the converter reaches DMIN_BOOST , given by: Light Load Current Operation The LTC3789 can be enabled to enter pulse-skipping mode or forced continuous conduction mode. To select forced continuous operation, tie the MODE/PLLIN pin to a DC voltage below 0.8V (e.g., SGND). To select pulse-skipping mode of operation, tie the MODE/PLLIN pin to INTVCC. When the LTC3789 enters pulse-skipping mode, in the boost region, synchronous switch D is held off whenever reverse current on the inductor is detected. At very light loads, the current comparator, ICMP , may remain tripped for several cycles and force switch C to stay off for the same number of cycles (i.e., skipping pulses). In the buck region, the inductor current is not allowed to reverse. Synchronous switch B is held off whenever reverse current on the inductor is detected. At very light loads, the current comparator, ICMP , may remain untripped for several cycles, holding switch A off for the same number of cycles. Synchronous switch B also remains off for the skipped cycles. In the buck-boost region, the controller operates alternatively in boost and buck region in one clock cycle, as in continuous operation. A small amount of reverse current is allowed, to minimize ripple. For the same reason, a narrow band of continuous buck and boost operation is allowed on the high and low line ends of the buck-boost region. Output Overvoltage
3789 F04b
1 DMIN _ BOOST = * 100% = 8.33% 12
Figure 5 shows typical boost region waveforms. If VIN approaches VOUT, the buck-boost region is reached.
CLOCK SWITCH A SWITCH B SWITCH C SWITCH D IL
3789 F04a
(4a) Buck-Boost Region (VIN VOUT)
CLOCK SWITCH A SWITCH B SWITCH C SWITCH D IL
(4b) Buck-Boost Region (VIN VOUT) Figure 4. Buck-Boost Region
CLOCK SWITCH A SWITCH B SWITCH C SWITCH D IL
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HIGH 0V
Figure 5. Boost Region (VIN << VOUT)
If the output voltage is higher than the value commanded by the VFB resistor divider, the LTC3789 will respond according to the mode and region of operation. In continuous conduction mode, the LTC3789 will sink current into the input. If the input supply is capable of sinking current, the LTC3789 will allow up to about 160mV/RSENSE to be sunk into the input. In pulse-skipping mode and in the buck or boost regions, switching will stop and the output will be allowed to remain high. In pulse-skipping mode, and in the buck/boost region as well as the narrow band of continuous boost operation that adjoins it, current sunk into the input through switchA is limited to approximately 40mV/ RDS(ON) of switch A. If this level is reached, switching will stop and the output will rise. In pulse-skipping mode, and in the narrow continuous buck region that adjoins the buck/ boost region, current sunk into the input through RSENSE is limited to approximately 40mV/RSENSE.
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LTC3789 operaTion
Constant-Current Regulation The LTC3789 provides a constant-current regulation loop for either input or output current. A sensing resistor close to the input or output capacitor will sense the input or output current. When the current exceeds the programmed current limit, the voltage on the ITH pin will be pulled down to maintain the desired maximum input or output current. The input current limit function prevents overloading the DC input source, while the output current limit provides a building block for battery charger or LED driver applications. It can also serve as an extra current limit protection for a constant-voltage regulation application. The input/ output current limit function has an operating voltage range of GND to the absolute maximum VOUT (VIN). Frequency Selection and Phase-Locked Loop (FREQ and MODE/PLLIN Pins) The selection of switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3789's controllers can be selected using the FREQ pin. If the MODE/PLLIN pin is not being driven by an external clock source, the FREQ pin can be used to program the controller's operating frequency from 200kHz to 600kHz. Switching frequency is determined by the voltage on the FREQ pin. Since there is a precision 10A current flowing out of the FREQ pin, the user can program the controller's switching frequency with a single resistor to SGND. A curve is provided in the Applications Information section to show the relationship between the voltage on the FREQ pin and the switching frequency. A phase-locked loop (PLL) is integrated on the LTC3789 to synchronize the internal oscillator to an external clock source driving the MODE/PLLIN pin. The controller operates in forced continuous mode when it is synchronized. The PLL filter network is integrated inside the LTC3789. The PLL is capable of locking to any frequency within the range of 200kHz to 600kHz. The frequency setting resistor should always be present to set the controller's initial switching frequency before locking to the external clock. Power Good (PGOOD) Pins The PGOOD pin is connected to the open drain of an internal N-channel MOSFET. When VFB is not within 10% of the 0.8V reference voltage, the PGOOD pin is pulled low. The PGOOD pin is also pulled low when RUN is below 1.22V or when the LTC3789 is in the soft-start phase. There is an internal 20s power good or bad mask when VFB goes in or out of the 10% window. The PGOOD pin is allowed to be pulled up by an external resistor to INTVCC or an external source of up to 6V. Short-Circuit Protection, Current Limit and Current Limit Foldback The maximum current threshold of the controller is limited by a voltage clamp on the ITH pin. In every boost cycle, the sensed maximum peak voltage is limited to 140mV. In every buck cycle, the sensed maximum voltage is limited to 90mV. In the buck-boost region, only peak sensed voltage is limited by the same threshold as in the boost region. The LTC3789 includes current foldback to help limit load current when the output is shorted to ground. If the output falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum value to one-third of the maximum value. Foldback current limiting is disabled during the soft-start. Under short-circuit conditions, the LTC3789 will limit the current by operating as a buck with very low duty cycles, and by skipping cycles. In this situation, synchronous switch B will dissipate most of the power (but less than in normal operation).
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LTC3789 applicaTions inForMaTion
The Typical Application on the first page is a basic LTC3789 application circuit. External component selection is driven by the load requirement, and begins with the selection of RSENSE and the inductor value. Next, the power MOSFETs are selected. Finally, CIN and COUT are selected. This circuit can be configured for operation up to an input voltage of 38V. RSENSE Selection and Maximum Output Current RSENSE is chosen based on the required output current. The current comparator threshold sets the peak of the inductor current in the boost region and the maximum inductor valley current in the buck region. In the boost region, the maximum average load current at VIN(MIN) is:
140mV IL VIN(MIN) * IOUT(MAX,BOOST) = - 2 VOUT RSENSE
The maximum current sensing RSENSE value for the boost region is: RSENSE(MAX) =
2 * 140mV * VIN(MIN) 2 * IOUT(MAX,BOOST) * VOUT + IL,BOOST * VIN(MIN)
The maximum current sensing RSENSE value for the buck region is: 2 * 90mV RSENSE(MAX) = 2 * IOUT(MAX,BUCK) - IL,BUCK The final RSENSE value should be lower than the calculated RSENSE(MAX) in both the boost and buck regions. A 20% to 30% margin is usually recommended. Programming Input/Output Current Limit As shown in Figures 7 and 8, current sense resistor RSENSE2 should be placed between the buck capacitor for VIN /VOUT and the decoupling capacitor. A lowpass filter formed by RF and CF is recommended to reduce the switching noise. The input/output current limit is set by the ILIM pin for 50mV, 100mV or 140mV with ILIM pulled to the GND, floating, or tied to INTVCC, respectively. If input/output current limit is not desired, the IOSENSE+ and IOSENSE- pins should be shorted to either VOUT or VIN.
FROM CONTROLLER VOUT RSENSE2 RF 100 2 IOSENSE+ LTC3789
3789 F07
where IL is peak-to-peak inductor ripple current. In the buck region, the maximum average load current is: IOUT(MAX,BUCK) = 90mV IL + 2 RSENSE
Figure 6 shows how the load current (ILOAD(MAX) * RSENSE) varies with input and output voltage.
160 150 ILOAD(MAX) * RSENSE (mV) 140 130 120 110 100 90 0.1 1 VIN /VOUT (V) 10
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CF
RF 100 1 IOSENSE-
+
TO SYSTEM VOUT
Figure 7. Programming Output Current Limit
FROM DC POWER INPUT RSENSE2 TO REMAINDER OF SYSTEM
+
RF 100 2 IOSENSE+
CF
RF 100 1 IOSENSE-
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Figure 6. Load Current vs VIN/VOUT
LTC3789
Figure 8. Programming Input Current Limit
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With the typical 100 resistors shown here, the value of . capacitor CF should be 1F to 2.2F The current loop's transfer function should approximate that of the voltage loop. Crossover frequency should be one-tenth the switching frequency, and gain should decrease by 20dB/decade. Similar current and voltage loop transfer functions will ensure overall system stability. When the IOSENSE common mode voltage is above ~3.2V, the IOSENSE- pin sources 10A. The IOSENSE+ pin, however, sources 18.3A, 26.6A and 35A when the ILIM pin is low, floating, and high, respectively, and when a constant current is being regulated. The error introduced by this mismatch can be offset to a first order by scaling the IOSENSE+ and IOSENSE- resistors accordingly. For example, if the IOSENSE+ branch has a 100 resistor, the 1.83mV across it can be replicated in the IOSENSE- branch by using a 182 resistor. When the IOSENSE common mode voltage falls below ~3.2V by a diode drop, the IOSENSE current decreases linearly; it reaches approximately -300A at zero volts. The values of the diode drop and maximum current sinking can vary by 20% to 30% due to process variation. Slope Compensation Slope compensation provides stability in constantfrequency architectures by preventing subharmonic oscillations at high duty cycles in boost operation and at low duty cycles in buck operation. This is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40% in the boost region, or subtracting a ramp from the inductor current signal at lower than 40% duty cycles in the buck region. Normally, this results in a reduction of maximum inductor peak current for duty cycles >40% in the boost region, or an increase of maximum inductor current for duty cycles <40% in the buck region. However, the LTC3789 uses a scheme that counteracts this compensating ramp, which allows the maximum inductor current to remain unaffected throughout all duty cycles. Phase-Locked Loop and Frequency Synchronization The LTC3789 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the top MOSFET of the controller to be locked to the rising edge of an external clock signal applied to the MODE/PLLIN pin. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false locking to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the internal filter network. There is a precision 10A of current flowing out of the FREQ pin. This allows a single resistor to SGND to set the switching frequency when no external clock is applied to the MODE/PLLIN pin. The internal switch between FREQ and the integrated PLL filter network is on, allowing the filter network to be at the same voltage on the FREQ pin. Operating frequency is shown in Figure 9 and specified in the Electrical Characteristics table. If an external clock is detected on the MODE/PLLIN pin, the internal switch previously mentioned will turn off and isolate the influence of the FREQ pin. Note that the LTC3789 can only be synchronized to an external
800 700 600 FREQUENCY (kHz) 500 400 300 200 100 0 0 0.5 1 1.5 2 FREQ PIN VOLTAGE (V) 2.5
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Figure 9. Relationship Between Oscillator Frequency and Voltage at the FREQ Pin
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clock whose frequency is within range of the LTC3789's internal VCO. This is guaranteed to be between 200kHz and 600kHz. A simplified block diagram is shown in Figure 10.
2.4V 5V 10A RSET FREQ EXTERNAL OSCILLATOR MODE/ PLLIN DIGITAL SYNC PHASE/ FREQUENCY DETECTOR
For a given ripple the inductance terms in continuous mode are as follows: L BOOST > VIN(MIN) 2 * VOUT - V IN(MIN) * 100 f * IOUT(MAX) * % Ripple * VOUT2 VOUT * VIN(MAX) - VOUT * 100 f * IOUT(MAX) * % Ripple * VIN(MAX) H,
L BUCK >
VCO
(
)
H
where: f is operating frequency, Hz % Ripple is allowable inductor current ripple VIN(MIN) is minimum input voltage, V VIN(MAX) is maximum input voltage, V VOUT is output voltage, V IOUT(MAX) is maximum output load current, A For high efficiency, choose an inductor with low core loss, such as ferrite. Also, the inductor should have low DC resistance to reduce the I2R losses, and must be able to handle the peak inductor current without saturating. To minimize radiated noise, use a toroid, pot core or shielded bobbin inductor. CIN and COUT Selection In the boost region, input current is continuous. In the buck region, input current is discontinuous. In the buck region, the selection of input capacitor CIN is driven by the need to filter the input square wave current. Use a low ESR capacitor sized to handle the maximum RMS current. For buck operation, the input RMS current is given by: IRMS IOUT(MAX) * VOUT VIN * -1 VIN VOUT
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Figure 10. Phase-Locked Loop Block Diagram
If the external clock frequency is greater than the internal oscillator's frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the filter network. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the filter network. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for the amount of time corresponding to the phase difference. The voltage on the filter network is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor holds the voltage. Typically, the external clock (on the MODE/PLLIN pin) input high threshold is 1.6V, while the input low threshold is 1V. Inductor Selection The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. The inductor value has a direct effect on ripple current. The inductor current ripple IL is typically set to 20% to 40% of the maximum inductor current in the boost region at VIN(MIN).
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor.
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In the boost region, the discontinuous current shifts from the input to the output, so COUT must be capable of reducing the output voltage ripple. The effects of ESR (equivalent series resistance) and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. The steady ripple due to charging and discharging the bulk capacitance is given by: Ripple (Boost,Cap) = IOUT(MAX) * ( VOUT - VIN(MIN) ) COUT * VOUT * f COUT * VIN(MAX) * f V In order to select the power MOSFETs, the power dissipated by the device must be known. For switch A, the maximum power dissipation happens in the boost region, when it remains on all the time. Its maximum power dissipation at maximum output current is given by: PA,BOOST V = OUT * IOUT(MAX) * t * RDS(ON) V
IN 2
Ripple (Buck,Cap) =
IOUT(MAX) * ( VIN(MAX ) - VOUT )
V
where t is a normalization factor (unity at 25C) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/C, as shown in Figure 11. For a maximum junction temperature of 125C, using a value t = 1.5 is reasonable.
2.0 T NORMALIZED ON-RESISTANCE ( )
where COUT is the output filter capacitor. The steady ripple due to the voltage drop across the ESR is given by: VBOOST,ESR = IL(MAX,BOOST) * ESR VBUCK,ESR = IL(MAX,BUCK) * ESR Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient. Capacitors are now available with low ESR and high ripple current ratings, such as OS-CON and POSCAP . Power MOSFET Selection and Efficiency Considerations The LTC3789 requires four external N-channel power MOSFETs, two for the top switches (switches A and D, shown in Figure 1) and two for the bottom switches (switches B and C, shown in Figure 1). Important parameters for the power MOSFETs are the breakdown voltage VBR,DSS, threshold voltage VGS,TH, on-resistance RDS(ON), reverse transfer capacitance CRSS and maximum current IDS(MAX). The drive voltage is set by the 5.5V INTVCC supply. Consequently, logic-level threshold MOSFETs must be used in LTC3789 applications.
1.5
1.0
0.5
0 -50
50 100 0 JUNCTION TEMPERATURE (C)
150
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Figure 11. Normalized RDS(ON) vs Temperature
Switch B operates in the buck region as the synchronous rectifier. Its power dissipation at maximum output current is given by: PB,BUCK = VIN - VOUT * IOUT(MAX) 2 * t * RDS(ON) VIN
Switch C operates in the boost region as the control switch. Its power dissipation at maximum current is given by:
PC,BOOST =
( VOUT - VIN ) VOUT
VIN
2
* IOUT(MAX) 2 * t * CRSS * f
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IOUT(MAX) VIN
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LTC3789 applicaTions inForMaTion
where CRSS is usually specified by the MOSFET manufacturers. The constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.7. For switch D, the maximum power dissipation happens in the boost region, when its duty cycle is higher than 50%. Its maximum power dissipation at maximum output current is given by:
PD,BOOST V = IN VOUT V * OUT * IOUT(MAX) * t * RDS(ON) V
IN 2
For the same output voltage and current, switch A has the highest power dissipation and switch B has the lowest power dissipation unless a short occurs at the output. From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following formula: TJ = TA + P * RTH(JA) The RTH(JA) to be used in the equation normally includes the RTH(JC) for the device plus the thermal resistance from the case to the ambient temperature (RTH(JC)). This value of TJ can then be compared to the original, assumed value used in the iterative calculation process. Schottky Diode (D1, D2) Selection The Schottky diodes, D1 and D2, shown in Figure 13, conduct during the dead time between the conduction of the power MOSFET switches. They are intended to prevent the body diode of synchronous switches B and D from turning on and storing charge during the dead time. In particular, D2 significantly reduces reverse recovery current between switch D turn-off and switch C turn-on, which improves converter efficiency and reduces switch C voltage stress. In order for the diode to be effective, the inductance between it and the synchronous switch must be as small as possible, mandating that these components be placed adjacently. INTVCC Regulators and EXTVCC The LTC3789 features a true PMOS LDO that supplies power to INTVCC from the VIN supply. INTVCC powers the
gate drivers and much of the LTC3789's internal circuitry. The linear regulator regulates the voltage at the INTVCC pin to 5.5V when VIN is greater than 6.5V. EXTVCC can supply the needed power when its voltage is higher than 4.8V through another on-chip PMOS LDO. Each of these can supply a peak current of 100mA and must be bypassed to ground with a minimum of 1F ceramic capacitor or low ESR electrolytic capacitor. No matter what type of bulk capacitor is used, an additional 0.1F ceramic capacitor placed directly adjacent to the INTVCC and PGND pins is highly recommended. Good bypassing is needed to supply the high transient current required by the MOSFET gate drivers and to prevent interaction between the channels. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3789 to be exceeded. The INTVCC current, which is dominated by the gate charge current, may be supplied by either the 5.5V linear regulator from VIN or the 5.5V LDO from EXTVCC . When the voltage on the EXTVCC pin is less than 4.5V, the linear regulator from VIN is enabled. Power dissipation for the IC in this case is highest and is equal to VIN * IINTVCC. The gate charge current is dependent on operating frequency, as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 3 of the Electrical Characteristics. For example, the LTC3789 INTVCC current is limited to less than 24mA from a 24V supply in the SSOP package and not using the EXTVCC supply: TJ = 70C + (28mA)(24V)(80C/W) = 125C To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (MODE/PLLIN = SGND) at maximum VIN. When the voltage applied to EXTVCC rises above 4.8V, the INTVCC linear regulator from VIN is turned off and the linear regulator from EXTVCC is turned on and remains on as long as the voltage applied to EXTVCC remains above 4.5V. Using EXTVCC allows the MOSFET driver and control power to be derived from the LTC3789's switching regulator output during normal operation and from the VIN when the output is out of regulation (e.g., start-up, short-circuit). Do not apply more than 14V to EXTVCC.
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Significant efficiency and thermal gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Switcher Efficiency). Tying the EXTVCC pin to a 12V output reduces the junction temperature in the previous example from 125C to 97C: TJ = 70C + (28mA)(12V)(80C/W) = 97C Powering INTVCC from the output can also provide enough gate drive when VIN drops below 5V. This allows a wider operating range for VIN after the controller start into regulation. The following list summarizes the three possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5.5V regulator at the cost of a small efficiency penalty. 2. EXTVCC connected directly to VOUT (4.7V < VOUT < 14V). This is the normal connection for the 5.5V regulator and provides the highest efficiency. 3. EXTVCC connected to an external supply. If an external supply is available in the 4.7V to 14V range, it may be used to power EXTVCC provided it is compatible with the MOSFET gate drive requirements. Note that there is an internal body diode from INTVCC to VIN. When INTVCC is powered from EXTVCC and VIN drops lower than 4.5V, the diode will create a back-feeding path from EXTVCC to VIN. To limit this back-feeding current, a 10 ~ 15 resistor is recommended between the system VIN voltage and the chip VIN pin. Output Voltage The LTC3789 output voltage is set by an external feedback resistive divider carefully placed across the output capacitor. The resultant feedback signal is compared with the internal precision 0.8V voltage reference by the error amplifier. The output voltage is given by the equation: R2 VOUT = 0.8V * 1+ R1 where R1 and R2 are defined in Figure 13. Topside MOSFET Driver Supply (CA, DA, CB, DB) Referring to Figure 13, the external bootstrap capacitors CA and CB connected to the BOOST1 and BOOST2 pins supply the gate drive voltage for the topside MOSFET switches A and D. When the top switch A turns on, the switch node SW2 rises to VIN and the BOOST2 pin rises to approximately VIN + INTVCC. When the bottom switch B turns on, the switch node SW2 drops to low and the boost capacitor CB is charged through DB from INTVCC. When the top switch D turns on, the switch node SW1 rises to VOUT and the BOOST1 pin rises to approximately VOUT + INTVCC. When the bottom switch C turns on, the switch node SW1 drops to low and the boost capacitor CA is charged through DA from INTVCC. The boost capacitors CA and CB need to store about 100 times the gate charge required by the top switches A and D. In most applications, a 0.1F to 0.47F X5R or X7R dielectric capacitor , is adequate. Undervoltage Lockout The LTC3789 has two functions that help protect the controller in case of undervoltage conditions. A precision UVLO comparator constantly monitors the INTVCC voltage to ensure that an adequate gate-drive voltage is present. It locks out the switching action when INTVCC is below 3.4V. To prevent oscillation when there is a disturbance on the INTVCC, the UVLO comparator has 400mV of precision hysteresis. Another way to detect an undervoltage condition is to monitor the VIN supply. Because the RUN pin has a precision turn-on reference of 1.22V, one can use a resistor divider to VIN to turn on the IC when VIN is high enough. An extra 5A of current flows out of the RUN pin once its voltage passes 1.22V. One can program the hysteresis of the run comparator by adjusting the values of the resistive divider. Soft-Start Function When a capacitor is connected to the SS pin, a soft-start current of 3A starts to charge the capacitor. A soft-start function is achieved by controlling the output ramp voltage according to the ramp rate on the SS pin. Current foldback is disabled during this phase to ensure smooth soft-start. When the chip is in the shutdown state with its RUN pin voltage below 1.22V, the SS pin is actively pulled
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LTC3789 applicaTions inForMaTion
to ground. The soft-start range is defined to be the voltage range from 0V to 0.8V on the SS pin. The total soft-start time can be calculated as: main sources account for most of the losses in LTC3789 circuits: 1. DC I2R losses. These arise from the resistances of the MOSFETs, sensing resistor, inductor and PC board traces and cause the efficiency to drop at high output currents. 2. Transition loss. This loss arises from the brief amount of time switch A or switch C spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input voltages above 20V and can be estimated from: Transition Loss 1.7A-1 * VIN2 * IOUT * CRSS * f where CRSS is the reverse transfer capacitance. 3. INTVCC current. This is the sum of the MOSFET driver and control currents. This loss can be reduced by supplying INTVCC current through the EXTVCC pin from a high efficiency source, such as the output (if 4.7V < VOUT < 14V) or alternate supply if available. 4. CIN and COUT loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator in buck mode. The output capacitor has the more difficult job of filtering the large RMS output current in boost mode. Both CIN and COUT are required to have low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. 5. Other losses. Schottky diodes D1 and D2 are responsible for conduction losses during dead time and light load conduction periods. Inductor core loss occurs predominately at light loads. Switch C causes reverse recovery current loss in boost mode. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If one makes a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency.
tSOFTSTART = 0.8 *
CSS 3A
Regardless of the mode selected by the MODE/PLLIN pin, the regulator will always start in pulse-skipping mode up to SS = 0.8V. Fault Conditions: Current Limit and Current Foldback The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the boost region, maximum sense voltage and the sense resistance determine the maximum allowed inductor peak current, which is: 140mV IL(MAX,BOOST) = RSENSE In the buck region, maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current, which is:
IL(MAX,BUCK) =
90mV RSENSE
To further limit current in the event of a short circuit to ground, the LTC3789 includes foldback current limiting. If the output falls by more than 50%, then the maximum sense voltage is progressively lowered to about one-third of its full value. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in circuit produce losses, four
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Design Example VIN = 5V to 18V VOUT = 12V IOUT(MAX) = 5A f = 400kHz Maximum ambient temperature = 60C Set the frequency at 400kHz by applying 1.2V on the FREQ pin (see Figure 7). The 10A current flowing out of the FREQ pin will give 1.2V across a 120k resistor to GND. The inductance value is chosen first based on a 30% ripple current assumption. In the buck region, the ripple current is: IL,BUCK = VOUT f *L V * 1 - OUT VIN IL,BUCK * 100 IOUT % Output voltage is 12V. Select R1 as 20k. R2 is: R2 = VOUT * R1 - R1 0.8
Select R2 as 280k. Both R1 and R2 should have a tolerance of no more than 1%. Selecting MOSFET Switches The MOSFETs are selected based on voltage rating and RDS(ON) value. It is important to ensure that the part is specified for operation with the available gate voltage amplitude. In this case, the amplitude is 5.5V and MOSFETs with an RDS(ON) value specified at VGS = 4.5V can be used.
IRIPPLE,BUCK =
The highest value of ripple current occurs at the maximum input voltage. In the boost region, the ripple current is:
I L,BOOST = V * 1 - IN f *L VOUT VIN I L,BOOST * 100 I IN %
Select QA and QB. With 18V maximum input voltage MOSFETs with a rating of at least 30V are used. As we do not yet know the actual thermal resistance (circuit board design and airflow have a major impact) we assume that the MOSFET thermal resistance from junction to ambient is 50C/W.
If we design for a maximum junction temperature, TJ(MAX) = 125C, the maximum RDS(ON) value can be calculated. First, calculate the maximum power dissipation: TJ(MAX) - TA(MAX) PD(MAX) = R(j- a) PD(MAX) = (125 - 60) = 1.3W 50
I RIPPLE,BOOST =
The highest value of ripple current occurs at VIN = VOUT/2. A 6.8H inductor will produce 11% ripple in the boost region (VIN = 6V) and 29% ripple in the buck region (VIN = 18V). The RSENSE resistor value can be calculated by using the maximum current sense voltage specification with some accommodation for tolerances.
RSENSE = 2 * 140mV * VIN(MIN) 2 * IOUT(MAX,BOOST) * VOUT + IL,BOOST * VIN(MIN)
The maximum dissipation in QA occurs at minimum input voltage when the circuit operates in the boost region and QA is on continuously. The input current is then: VOUT * IOUT(MAX) , OR 12A VIN(MIN) We calculate a maximum value for RDS(ON): RDS(ON) (125C) < RDS(ON) (125C) < PD(MAX) IIN(MAX) 2 1.3W (12A)2 = 0.009
Select an RSENSE of 10m.
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22
LTC3789 applicaTions inForMaTion
The Vishay SiR422DP has a typical RDS(ON) of 0.010 at TJ = 125C and VGS = 4.5V. The maximum dissipation in QB occurs at maximum input voltage when the circuit is operating in the buck region. The dissipation is:
P B,BUCK = VIN - VOUT * IOUT(MAX) 2 * t * RDS(ON) VIN 1.3W 18V TO -12V 18V * (5A)
2
The dissipation in switch QD is:
V P D,BOOST = * OUT * IOUT(MAX) VOUT VIN * t * RDS(ON) VIN
2
Vishay SiR484OY is a possible choice for QC and QD. The calculated power loss at 5V input voltage is then 1.3W for QC and 0.84W for QD. CIN is chosen to filter the square current in the buck region. In this mode, the maximum input current peak is: 29% IIN,PEAK(MAX,BUCK) = 5A * 1+ = 5.7A 2 A low ESR (10m) capacitor is selected. Input voltage ripple is 57mV (assuming ESR dominates the ripple). COUT is chosen to filter the square current in the boost region. In this mode, the maximum output current peak is: IOUT,PEAK(MAX,BOOST) = 11% 12 * 5 * 1+ = 10.6A 5 2
R DS(ON)(125C) <
= 0.156
This seems to indicate that a quite small MOSFET can be used for QB if we only look at power loss. However, with 5A current the voltage drop across 0.156 is 0.78V, which means the MOSFET body diode is conducting. To avoid body diode current flow we should keep the maximum voltage drop well below 0.5V, using, for example, Vishay Si4840BDY in the SO-8 package (RDSON(MAX) = 0.012).
Select QC and QD. With 12V output voltage we need MOSFETs with 20V or higher rating.
The highest dissipation occurs at minimum input voltage when the inductor current is highest. For switch QC the dissipation is: PC,BOOST = * IOUT(MAX) (VOUT - VIN )VOUT VIN
2 2
A low ESR (5m) capacitor is suggested. This capacitor will limit output voltage ripple to 53mV (assuming ESR dominates the ripple). PC Board Layout Checklist The basic PC board layout requires a dedicated ground plane layer. Also, for high current, a multilayer board provides heat sinking for power components. * The ground plane layer should not have any traces and should be as close as possible to the layer with power MOSFETs. * Place CIN, switch A, switch B and D1 in one compact area. Place COUT, switch C, switch D and D2 in one compact area. One layout example is shown in Figure 12. * Use immediate vias to connect the components (including the LTC3789's SGND and PGND pins) to the ground plane. Use several large vias for each power component.
* t * RDS(ON) IOUT(MAX) VIN * CRSS * f
+ k * VOUT 3 *
where CRSS is usually specified by the MOSFET manufacturers. The constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.7.
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23
LTC3789 applicaTions inForMaTion
* Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. * Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to any DC net (VIN or GND). When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3789. These items are also illustrated in Figure 13. * Segregate the signal and power grounds. All smallsignal components should return to the SGND pin at one point, which is then tied to the PGND pin close to the inductor current sense resistor RSENSE. * Place switch B and switch C as close to the controller as possible, keeping the PGND, BG and SW traces short. * Keep the high dV/dT SW1, SW2, BOOST1, BOOST2, TG1 and TG2 nodes away from sensitive small-signal nodes. * The path formed by switch A, switch B, D1 and the CIN capacitor should have short leads and PC trace lengths. The path formed by switch C, switch D, D2 and the COUT capacitor also should have short leads and PC trace lengths.
VIN SW2 L QA D1 QB CIN QC COUT SW1 D2 QD VOUT
* The output capacitor (-) terminals should be connected as closely as possible to the (-) terminals of the input capacitor. * Connect the top driver boost capacitor CA closely to the BOOST1 and SW1 pins. Connect the top driver boost capacitor CB closely to the BOOST2 and SW2 pins. * Connect the input capacitors CIN and output capacitors COUT closely to the power MOSFETs. These capacitors carry the MOSFET AC current in the boost and buck region. * Connect VFB pin resistive dividers to the (+) terminals of COUT and signal ground. A small VFB bypass capacitor may be connected closely to the LTC3789 SGND pin. The R2 connection should not be along the high current or noise paths, such as the input capacitors. * Route SENSE- and SENSE+ leads together with minimum PC trace spacing. Avoid having sense lines pass through noisy areas, such as switch nodes. The filter capacitor between SENSE+ and SENSE- should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the SENSE resistor. One layout example is shown in Figure 14. * Connect the ITH pin compensation network closely to the IC, between ITH and the signal ground pins. The capacitor helps to filter the effects of PCB noise and output voltage ripple voltage from the compensation loop. * Connect the INTVCC bypass capacitor, CVCC, closely to the IC, between the INTVCC and the power ground pins. This capacitor carries the MOSFET drivers' current peaks. An additional 1F ceramic capacitor placed immediately next to the INTVCC and PGND pins can help improve noise performance substantially.
RSENSE LTC3789 CKT GND
3789 F12
Figure 12. Switches Layout
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24
LTC3789 applicaTions inForMaTion
R1 20k R2 280k VPULLUP VOUT 1 2 CC2 1000pF CC1 3300pF RC 68k 3 4 5 6 7 121k ON/OFF VIN VOUT 8 9 10 11 12 13 27 26 25 24 23 22 21 INTVCC 20 19 18 CB 0.22F VOUT DB DFLS160 DA DFLS160 CF 1F CVCC 4.7F 10m CA 0.22F QA Si7884DP L 6.8H D2 B240A 10 VIN 5V TO 38VMAX CIN 47F
CSS 6.8nF
VFB PGOOD SS SENSE+ SENSE- ITH SGND FREQ RUN VINSNS VOUTSNS ILIM LTC3789
SW1 TG1 BOOST1 PGND BG1 VIN INTVCC EXTVCC BG2 BOOST2
QB Si7884DP
MODE/PLLIN
QC Si7884DP D1 B240A
IOSENSE+ 2.2F 14 I - OSENSE
TG2 SW2 TRIM
17 16 15
QD Si7884DP
COUT 2.2F 10m VOUT 12V, 5A 330F
100 100 1k 1k
3789 F13
+
Figure 13. LTC3789 12V/5A, Buck-Boost Regulator
PGND RSENSE 28 27 26 25 24 23 22 21 20 19
18
17 12
16 13 C R
10
11
SGND
3789 F14
Figure 14. Sense Lines Layout
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14 R
1
2
3
4
5
6
7
8
9
15
25
LTC3789 package DescripTion
GN Package 28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005
.386 - .393* (9.804 - 9.982) 28 27 26 25 24 23 22 21 20 19 18 17 1615
.033 (0.838) REF
.254 MIN
.150 - .165
.229 - .244 (5.817 - 6.198)
.150 - .157** (3.810 - 3.988)
.0165 .0015 RECOMMENDED SOLDER PAD LAYOUT
.0250 BSC
1 .0532 - .0688 (1.35 - 1.75)
23
4
56
7
8
9 10 11 12 13 14 .004 - .0098 (0.102 - 0.249)
.015 .004 45 (0.38 0.10) .0075 - .0098 (0.19 - 0.25) .016 - .050 (0.406 - 1.270)
NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE 0 - 8 TYP
.008 - .012 (0.203 - 0.305) TYP
.0250 (0.635) BSC
GN28 (SSOP) 0204
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
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26
LTC3789 package DescripTion
(Reference LTC DWG # 05-08-1712 Rev B)
UFD Package 28-Lead Plastic QFN (4mm x 5mm)
0.70 0.05
4.50 0.05 3.10 0.05 2.50 REF 2.65 0.05 3.65 0.05
PACKAGE OUTLINE
0.25 0.05 0.50 BSC 3.50 REF 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER 27 28 0.40 0.10 1 2 5.00 0.10 (2 SIDES)
2.50 REF R = 0.115 TYP
3.50 REF 3.65 0.10 2.65 0.10
(UFD28) QFN 0506 REV B
0.200 REF 0.00 - 0.05
0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD
NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC3789 Typical applicaTion
24V/5A Buck-Boost Regulator
VOS+ RFB1 232k RFB2 8.06k R9, 1.24k C11, OPT 1 2 0.01F 3 4 R10, 1.24k CC2, 0.01F VIN R5 10 , 0805 INTVCC R7 100k SW1 TG1 BOOST1 PGND1 BG1 VIN 27 26 25 24 23 22 INTVCC 21 20 19 18 C24, 1F D2 D7 DFLS160 3 BAS16 1 R1, 5.6 C22 0.22F, 16V C18 10F, 1206 R11, 0 C4 0.22F, 16V D4 DFLS160 Q4 Si4840BDY D5 B240A C15 1F 50V 1210 C6 3.3F 50V 1210 J3
+
CIN1 270F 50V OPT
+
CIN2 270F 50V
VIN 9V TO 35V
VOS+ C1 R2 2.2F, 0.010 50V 2% X5R D6 B240A
VOUT
J1 COUT2 330F 34V R8 10
+
VOUT 24V AT 5A
28 VFB SS SENSE1+ SENSE1-
PGOOD
Q2 SiR422DP
Q3 SiR422DP
VOS+
CC1, 1000pF 5 ITH RC, 15k 6
L1 5.5H
C3 2.2F 50V X5R
VIN
R30 + 68.1k R31 12.1k
D8 BZX84C5V1 C7, 0.1F C8, 0.1F
R21 121k, 1%
7 8 9 10 11 12
LTC3789EGN SGND FREQ RUN VINSNS VOUTSNS ILIM IOSENSE+ IOSENSE-
MODE/PLLIN INTVCC EXTVCC BG2 BOOST2
Q5 SiR422DP
R25 0 R14 100 VOUT VIN
R13, 100
13
C10, 2.2F 14
TG2 SW2 TRIM
17 16 15 VOUT
R18 8m 2% R4, 100 R3, 100 L1: WURTH 7443630550
3789 TA02
relaTeD parTs
PART NUMBER LTC3780 LTC3785 LTM4605 LTM4607 LTM4609 LTC3533 DESCRIPTION High Efficiency (Up to 98%) Synchronous, 4-Switch Buck-Boost DC/DC Controller High Efficiency (Up to 98%) Synchronous, 4-Switch Buck-Boost DC/DC Controller High Efficiency Buck-Boost DC/DC ModuleTM High Efficiency Buck-Boost DC/DC Module High Efficiency Buck-Boost DC/DC Module 2A Synchronous Buck-Boost Monolithic DC/DC Converter COMMENTS 4V VIN 36V, 0.8V VOUT 30V, 5mm x 5mm QFN-32 and SSOP-24 Packages 2.7V VIN 30V, 2.7V VOUT 10V, 4mm x 4mm QFN-24 Package 4.5V VIN 20V, 0.8V VOUT 16V, 15mm x 15mm x 2.8mm LGA Package 4.5V VIN 36V, 0.8V VOUT 25V, 15mm x 15mm x 2.8mm LGA Package 4.5V VIN 36V, 0.8V VOUT 34V, 15mm x 15mm x 2.8mm LGA Package 1.8V VIN 5.5V, 1.8V VOUT 5.25V, IQ = 40A, ISD < 1A, 3mm x 4mm DFN-14 Package
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28 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT 1210 * PRINTED IN USA
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2010

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